The Team of the TETRA project is composed of two project leaders, several researchers and guest researchers.
Francisco J. Alfaro is since July 2007 a full-time associate professor at the Universidad de Castilla-La Mancha in the Departamento de Sistemas Informáticos. He has published twenty two papers in ranked technical journals and more than 50 papers in international peer-reviewed conferences. He has been a member of the program committees of several international conferences and workshops in the interconnection field. He has advised 5 PhD students. Currently, he advises other 2 PhD students. His main current research topics are:
- High performance (off-chip) interconnects: InfiniBand-like networks, addressing routing algorithms, congestion management techniques, fault-tolerant algorithms, and quality of service provision. High-radix switch design including new topologies, routing algorithms, fault-tolerant algorithms, etc.
- Networks on chip: Routing algorithms and their implementations, addressing new challenges when building on-chip networks, including fault-tolerance, power management issues, virtualization, etc. New router architectures and topologies for on-chip networks. Congestion management in on-chip networks. Router designs for efficient on-chip interconnects. On-chip networks for embedded systems (addressing heterogeneity).
conferences and workshops, such as ICPP, HotI, CCGrid, ISC, HiPINEB. He has been also a guest editor of several journals.
Francisco José Quiles is a Full Professor of Computer Architecture and Technology at the Computing Systems Department of UCLM. His research interests include: high-performance interconnection networks for multiprocessor systems and clusters, parallel algorithms for video compression and video transmission. He has served as Program Committee member in several conferences. He has published over 200 papers in international journals and conferences and participated in 68 research projects supported by the NFS, European Commission, the Spanish Government and Research & Development Agreements with different companies. Also, he has supervised 9 doctoral theses.
José Luis Sánchez is an Associate Professor at UCLM. He has focused his research on developing several techniques to improve some aspects of the high-speed interconnection networks. In particular, he has worked on switch architecture, network reconfiguration, quality of service and energy consumption. He has been the coordinator of 10 research projects, supported by national and regional Spanish Governments, besides participating in other research projects, some of them supported by the European Commission.
Jesús Escudero Sahuquillo received the MS and PhD degrees in Computer Science from the University of Castilla-La Mancha (UCLM), Spain, in 2008 and 2011, respectively. In 2006 he joined the Computer Systems Department (DSI), UCLM, Spain. In 2014 he moved to the industry and worked for Oracle Corporation (Norway), as a PhD Senior Engineer. In 2015 he moved to the Technical University of Valencia (Spain), as a PostDoc research assistant granted with a national-competitive grant “Juan de La Cierva”. In 2016 he joined again the DSI, UCLM (Spain), with a 5-year PostDoc position, funded by the UCLM and the European Commission (FSE funds). His research interests include high-performance computing and Big-Data, interconnection networks and all the strategies related to improve them, such as network topologies, routing algorithms, congestion management, and power saving. He has published more than 30 papers in national and international peer-reviewed conferences and journals. Currently, he supervises two PhD students. He has participated in several research projects funded by the Spanish and the Castilla-La Mancha Government, as well as in R&D agreements with different companies. He serves as program committee member and reviewer in several conferences (HoTI, ICPP or CCGrid) and journals (TPDS, JPDC, JSC, CCPE, IEEE Micro, etc). He is co-organizer of the IEEE HiPINEB workshop.
Juan José García-Castro Crespo is a PhD student at the University of Castilla-La Mancha. His research activity focuses on networks-on-chip (NoCs), giving as a result 3 publications in national conferences and 2 in international conferences. His scientific trajectory goes from the analytical study of silicon integrated photonics for performance improvement and energy efficiency; to NoCs reconfiguration and partitioning on Chips Multi-Processor (CMPs) comprising thousand of computing resources. Graduated in Computer Science in 2015 by the University of Castilla-La Mancha. He also got his master studies by the same organization in 2017. His research experience is based on its work at the RAAP Research Group from the University of Castilla-La Mancha where he develops its current PhD studies. The Education Ministry of Spain provided Juan José with a national grant for university teacher training with ref. FPU15/03627, for its PhD development.
Javier Cano Cano received a degree in computer science from University of Castilla-La Mancha of Albacete, Spain. This year he joined to I3A as researcher. In 2016 he was admitted on the Ph.D program “PhD in Information Technology Advanced (Verified by R.D. 99/2011)”. In 2017 he got a FPI predoctoral grant with a deadline in 2021. During 2017 he finished the final master project called “CVefGem: Desarrollo de una herramienta de caracterización de aplicaciones para redes de altas prestaciones dentro del chip”, he got the highest mark (with honors). Nowadays, he work on his Ph.D thesis which is focused on off chip high performance interconnection networks.
Pedro Yébenes Segura is a Ph.D. student from the University of Castilla-La Mancha in Spain. He has worked in the High-Performance Networks and Architectures research group since 2011. He has participated in several research projects, both regional and national. In 2014, he was awarded with a scholarship from the Spanish government to carry out his doctorate. At the beginning of 2015, he did an internship in BULL/ATOS Company in Paris, France, which develops supercomputers using its BXI technology. He is the main developer of a simulator based on OMNeT++ framework to evaluate the performance of HPC networks. Moreover, it is used in the research group of the University of Heidelberg in Germany. His research focuses on the study of HPC networks that interconnects supercomputers and datacenters. His contributions are proposals that improve the performance of hybrid and hierarchical topologies, such as the KNS, the Dragonfly, and Slim Fly ones, in congestion situations, when the systems has several levels of priority for applications, when adversarial traffic cases appears, or both. All these results have been published in international journals and conferences. Moreover, he is the inventor of a national patent and an international one.
Germán Maglione Mathey received the BS and MS degrees in Computer Science from the University of Castilla-La Mancha (UCLM), Spain, in 2015 and 2016 respectively. He began his research career in 2015 as a PhD Student at the University of Castilla-La Mancha in Spain, when he was recruited by the Computer Architecture Department of that University. His research interests include High Performance Computing interconnects and Data Center Networks and all the strategies related to improve them, especially network topologies, routing algorithms and congestion management.
José Manuel Rocher González
Jose Francisco Duato Marín is Professor in the Department of Computer Engineering (DISCA) at the Technical University of Valencia.His current research interests include interconnection networks, on-chip networks, and multicore and multiprocessor architectures. He published over 500 refereed papers. According to Google Scholar, his publications received more than 13,000 citations. He proposed a theory of deadlock-free adaptive routing that has been used in the design of the routing algorithms for the Cray T3E supercomputer, the on-chip router of the Alpha 21364 microprocessor, and the IBM BlueGene/L supercomputer. He also developed RECN, a scalable congestion management technique, and a very efficient routing algorithm for fat trees that has been incorporated into Sun Microsystem’s 3456-port InfiniBand Magnum switch. Prof. Duato led the Advanced Technology Group in the HyperTransport Consortium, and was the main contributor to the High Node Count HyperTransport Specification 1.0. He also led the development of rCUDA, which enables remote virtualized access to GP-GPU accelerators using a CUDA interface. Prof. Duato is the first author of the book “Interconnection Networks: An Engineering Approach”. He also served as a member of the editorial boards of IEEE Transactions on Parallel and Distributed Systems, IEEE Transactions on Computers, and IEEE Computer Architecture Letters. Prof. Duato was awarded with the National Research Prize in 2009 and the “Rey Jaime I” Prize in 2006.
Eitan Zahavi manages the Mellanox end-to-end performance architecture group which focuses on features that improve the overall system performance for both Ethernet and InfiniBand, lossy and lossless. We also study Optical Data Center networks. Example fields of research are Application performance, Congestion Control, Adaptive Routing, Tenants Isolation, and Topologies. The group employs large system simulation and lab experiments to validate our hypothesis and test new features implementations.
Wainer Vandelli is, since 2015, a permanent Applied Physicist at CERN, Switzerland, mainly supporting the CERN contribution to the ATLAS experiment data-acquisition system. The project involves about twenty different institutions, universities and research centers. Members are based both at CERN and at their home institutes. He supervises the daily system functioning, the hardware upkeep and replacement as well as the progress of the upgrade sub-projects. He is also part of the CERN hierarchy as Section Leader of the CERN ATLAS data-acquisition group. The team is composed by about thirteen members, ranging from trainees to CERN permanent staffs, mainly with physics or computer engineer background. He is responsible for direct or indirect supervision of the team members, for the technical leadership and steering as well as hiring and appraisals. He directly manages the team budgets. Since his first employment at CERN as Early-Stage Training Marie-Curie Fellow in 2007, he has been contributing to many different aspects of the ATLAS data-acquisition system, with a growing level of responsibility. He developed high-performance distributed software applications, designed, procured and installed large storage systems and the associated software. He also lectures for the CERN Summer Student Programme and for the International School of Data-Acquisition. He served as lead reviewer for the Cherenkov Telescope Array project and contributed regularly to paper reviews for several journals.
Gaspar Mora Porta is currently part of the architecture team designing and developing next-generation Intel Omnipath products, where he is focusing on architecting a high-performance routing chip that will power future supercomputers. He received his PhD degree from the Universitat Politècnica de València (Spain) in 2009, and joined Intel Corporation in Santa Clara, California. Gaspar presently holds two granted US patents and has 5 patent applications.
Torsten Hoefler is an Assistant Professor of Computer Science at ETH Zürich, Switzerland. Before joining ETH, he led the performance modeling and simulation efforts of parallel petascale applications for the NSF-funded Blue Waters project at NCSA/UIUC. He is also a key member of the Message Passing Interface (MPI) Forum where he chairs the “Collective Operations and Topologies” working group. Torsten won best paper awards at the ACM/IEEE Supercomputing Conference SC10, SC13, SC14, EuroMPI 2013, IPDPS 2015, and other conferences. He published numerous peer-reviewed scientific conference and journal articles and authored chapters of the MPI-2.2 and MPI-3.0 standards. He received the Latsis award of ETH Zurich as well as an ERC starting grant in 2015. His research interests revolve around the central topic of “Performance-centric System Design” and include scalable networks, parallel programming techniques, and performance modeling.