En los últimos años, ha crecido enormemente la demanda, desde diversos ámbitos de la sociedad, de servicios TIC avanzados, tales como la supercomputación o el proceso y análisis de conjuntos masivos de datos (Big-Data). Está previsto que esta demanda continúe aumentando hasta tal punto que, por ejemplo, se estima que en el año 2020 los supercomputadores deberían ofrecer una potencia 10 veces superior a la actual (alcanzando el nivel Exascale) para satisfacer las necesidades de sus usuarios. En general, en el futuro cercano los sistemas que soporten servicios TIC avanzados sólo podrán ofrecer las prestaciones demandadas aumentando considerablemente el número de nodos de procesamiento y/o almacenamiento que los componen. En consecuencia, las redes que interconecten dichos nodos deberán ser mucho más eficientes que las de los sistemas actuales, para soportar necesidades de comunicación mucho mayores, sin que se dispare su coste y su consumo energético. Por ese motivo, tanto desde la industria como desde la academia se vienen realizando grandes esfuerzos en I+D orientados a acercar la eficiencia de las tecnologías de red de interconexión a las exigencias de futuros sistemas. En este sentido, en este proyecto se propone desarrollar técnicas que, desde diversos aspectos del diseño de la red, mejoren la eficiencia y el aprovechamiento de las tecnologías punteras de redes de interconexión, de cara a facilitar la configuración de infraestructuras de red capaces de interconectar eficientemente un mayor número de nodos de computación y/o almacenamiento.

Efficient Techniques for Advanced Interconnect Technologies

In the last years, different sides of the society increasingly demand advanced ICT services such as supercomputing, or the processing and analysis of massive amounts of data (Big-Data). It is expected that this demand will continue growing so that, for instance, by the year 2020 supercomputers should offer a computational power ten times greater than the current one (reaching so the Exascale level), in order to satisfy the estimated needs of the users. In general, in the near future, the number of processing and storage nodes included in the systems supporting advanced ICT services will have to increase, in order to meet the expected performance requirements. Hence, the networks interconnecting these nodes will have to be much more efficient than current ones, in order to support much greater communication needs while preventing cost and energy consumption from skyrocketing. For these reasons, both the industry and the academia are devoting great R&D efforts focused on bringing the efficiency of interconnect technologies closer to the requirements of future systems. In that sense, in this project we propose developing techniques that, from different aspects of the network, improve the efficiency and exploitation of leading interconnection-network technologies, in order to allow the configuration of network infrastructures able to efficiently interconnect a higher number of computing and storage nodes. The proposed research team consists of academic members with a wide experience in the field of interconnection networks, as well as experts from companies that are currently developing and producing high-performance interconnect technologies.

Research Team

  • Francisco J. Alfaro iD icon dblp.icon.18x18 Full Professor at the Universidad de Castilla-La Mancha.
  • Pedro Javier García iD icon dblp.icon.18x18 Full Professor at the Universidad de Castilla-La Mancha.
  • Francisco José Quiles iD icon dblp.icon.18x18 Full Professor at the Universidad de Castilla-La Mancha.
  • José Luis Sánchez iD icon dblp.icon.18x18 Full Professor at the Universidad de Castilla-La Mancha.
  • Jesús Escudero Sahuquillo iD icon  Associate Profesor at the Universidad de Castilla-La Mancha.
  • Juan José García-Castro Crespo. dblp.icon.18x18 Engineer at ARM Ltd.
  • Javier Cano Cano. Software Engineer at Red Hat.
  • Pedro Yébenes Segura dblp.icon.18x18Silicon Architecture Engineer at Intel Corporation
  • Germán Maglione Mathey iD icon dblp.icon.18x18Senior Software Engineer at Red Hat.
  • Jose Manuel Rocher González. dblp.icon.18x18 Consultant at Simula Research Laboratory.
  • José Duato Marín.   Qsimov CTO.
  • Eitan Zahavi. Distinguished Architectat Nvidia Corporation.
  • Gaspar Mora Porta.  Senior Architect at Nvidia Corporation.
  • Torsten Hoefler Full Professor at the ETH Zürich.

PhD Thesis

  • New Queuing Schemes to Improve the Efficiency of Hybrid and Hierarchical High-Performance Interconnection Network Topologies
    Student: Pedro Yébenes Segura. Advisors: Jesús Escudero Sahuquillo y Pedro Javier Garcia García. Reading date: 05/11/2018.
  • Habilitación de calidad de servicio en arquitecturas de switch jerárquico
    Student: Javier Cano Cano. Advisors: Francisco José Alfaro Cortés y Francisco José Andújar Muñoz.Reading date: 07/10/2021.
  • Efficient routing, job-isolation and congestion control techniques in commercial interconnection networks
    Student:German Horacio Maglione Mathey. Advisors: Jesús Escudero Sahuquillo y Pedro Javier Garcia García. Planned reading date: 18/10/2021.
  • Upstream Progressive Network Reconfiguration Schemes for High Performance Networks
    Student: Juan José García-Castro Crespo. Advisors: Francisco José Alfaro Cortés, José Luis Sánchez García y José Flich Cardo. Planned reading date: /11/2021.

Journals

  • Javier Cano-Cano, Francisco J. Andújar, Francisco J. Alfaro-Cortés, José L. Sánchez. Enabling Quality of Service Provision in Omni-Path Switches. Computational and Mathematical Methods, p. e1147, John Wiley & Sons, Ltd, (2021). doi:10.1002/CMM4.1147

  • Cristina Olmedilla, Jesus Escudero-Sahuquillo, Pedro Javier Garcia-Garcia, Francisco Alfaro-Cortes, Jose L. Sanchez, Francisco J. Quiles, Wenhao Sun, Xiang Yu, Yonghui Xu, Jose Duato. DVL-Lossy: Isolating congesting flows to optimize packet dropping in lossy data-center networks. IEEE Micro 41(1), p. 37-44, IEEE Computer Society (2021), doi:10.1109/MM.2020.3042263

  • Javier Cano-Cano, Francisco J. Andújar, Jesús Escudero-Sahuquillo, Francisco J. Alfaro-Cortés, José L. Sánchez. A methodology to enable QoS provision on InfiniBand hardware. The Journal of Supercomputing 2021 77:9 77(9), p. 9934-9946, Springer (2021). url, doi:10.1007/S11227-021-03667-X
  • Javier Cano-Cano, Francisco J. Andújar, Francisco J. Alfaro-Cortés, José L. Sánchez. QoS provision in hierarchical and non-hierarchical switch architectures. Journal of Parallel and Distributed Computing 148, p. 138-150, Academic Press (2021). doi:10.1016/J.JPDC.2020.10.009

  • Jose Rocher-Gonzalez, Jesus Escudero-Sahuquillo, Pedro J. García, Francisco J. Quiles, Gaspar Mora. Towards an efficient combination of adaptive routing and queuing schemes in Fat-Tree topologies. Journal of Parallel and Distributed Computing 147, p. 46-63, Academic Press (2021). doi:10.1016/J.JPDC.2020.07.009

  • German Maglione-Mathey, Jesus Escudero-Sahuquillo, Pedro Javier Garcia, Francisco J. Quiles, Eitan Zahavi. Leveraging InfiniBand controller to configure deadlock-free routing engines for Dragonflies. Journal of Parallel and Distributed Computing 147, p. 16-33, Academic Press. (2021) doi:10.1016/J.JPDC.2020.07.010

  • Juan-José Crespo, José L. Sánchez, Francisco J. Alfaro-Cortés, José Flich, José Duato. UPR: deadlock-free dynamic network reconfiguration by exploiting channel dependency graph compatibility. The Journal of Supercomputing 2021, p. 1-31, Springer (2021) doi:10.1007/S11227-021-03791-8
  • German Maglione-Mathey, Jesus Escudero-Sahuquillo, Pedro Javier Garcia, Francisco J. Quiles, Jose Duato. Path2SL: Leveraging InfiniBand resources to reduce head-of-line blocking in fat trees. IEEE Micro 40(1), p. 8-14, IEEE Computer Society, (2020), doi:10.1109/MM.2019.2949280
  • John Gliksberg, Antoine Capra, Alexandre Louvet, Pedro Javier Garcia, Devan Sohier. High-quality fault resiliency in fat trees
    IEEE Micro 40(1), p. 44-49, IEEE Computer Society, (2020), doi:10.1109/MM.2019.2949978
  • Francisco J. Andújar, Juan A. Villar, José L. Sánchez, Francisco J. Alfaro, José Duato, Holger Fröning. Constructing virtual 5-dimensional tori out of lower-dimensional network cards. Concurrency Computation 31(2), p. e4361, John Wiley and Sons Ltd (2019). doi:10.1002/cpe.4361
  • Javier Cano-Cano, Francisco J. Andújar, Francisco J. Alfaro, José L. Sánchez. Speeding up exascale interconnection network simulations with the VEF3 trace framework. Journal of Parallel and Distributed Computing 133, p. 124-135, Academic Press Inc. (2019). doi:10.1016/j.jpdc.2019.06.013
  • Juan Jose Crespo, José L. Sánchez, Francisco J. Alfaro-Cortés. Silicon photonic networks: Signal loss and power challenges. Concurrency Computation 31(21), p. 1-14 (2019), doi:10.1002/cpe.4777
  • Pedro Yebenes, Jose Rocher-Gonzalez, Jesus Escudero-Sahuquillo, Pedro Javier Garcia, Francisco J. Alfaro, Francisco J. Quiles, Crispín Gómez, Jose Duato. Combining Source-adaptive and Oblivious Routing with Congestion Control in High-performance Interconnects using Hybrid and Direct Topologies. ACM Transactions on Architecture and Code Optimization 16(2), p. 1-26, Association for Computing Machinery (2019). doi:10.1145/3319805
  • Escudero, P.J. García, F.J. Quiles, J. Duato, G. Maglione. Feasible enhancements to congestion control in InfiniBand-based networks. Journal of Parallel and Distributed Computing (2018). doi:10.1016/j.jpdc.2017.09.008
  • Maglione, P. Yébenes, J. Escudero, P.J. García, F.J. Quiles, E. Zahavi. Scalable Deadlock-free Deterministic Minimal-Path Routing Engine for InfiniBand-Based Dragonfly Networks. IEEE Transactions on Parallel and Distributed Systems (2018) doi:10.1109/TPDS.2017.2742503

International Conferences

  • JM. Rocher, J. Escudero, P.J. García, F.J. Quiles, G. Mora. Efficient Congestion Management for High-Speed Interconnects using Adaptive Routing. CCGRID 2019: 221-230
  • Crespo, J. J., Maglione-Mathey, G., Sanchez, J. L., Alfaro-Cortes, F. J., Escudero-Sahuquillo, J., Garcia, P. J., & Quiles, F. J. (2019, July). Methodology for Decoupled Simulation of SystemVerilog HDL Designs. In 2019 International Conference on High Performance Computing & Simulation (HPCS) (pp. 741-746). IEEE. https://doi.org/10.1109/hpcs48598.2019.9188056
  • J. Gliksberg, A. Capra, A. Louvet, P. J. Garcia, and D. Sohier: “Dmodc: High-Quality Fault-Resiliency in Fat-Tree Networks”. 26th Simposium on High-Performance Interconnects (HOTI),  August 2019, Santa Clara (EEUU).
  • Luis Gonzalez-Naharro, Jesús Escudero-Sahuquillo, Pedro Javier Garcia, Francisco J. Quiles, Jose Duato, Wenhao Sun, Li Shen, Xiang Yu and Hewen Zheng. Efficient Dynamic Isolation of Congestion in Lossless DataCenter Networks. ACM SIGCOMM 2019 Workshop on Networking for Emerging Applications and Technologies (NEAT), August 2019, Beijing, China.
  • Luis Gonzalez-Naharro, Jesús Escudero-Sahuquillo, Pedro Javier García, Francisco José Quiles Flor, José Duato, Wenhao Sun, Li Shen, Xiang Yu, Hewen Zheng: Modeling Traffic Workloads in Data-center Network Simulation Tools. HPCS 2019, Dublin, Ireland.
  • Felix Zahn, Pedro Yebenes, Jesus Escudero-Sahuquillo, Pedro Javier Garcia and Holger Froening. Effects of Congestion Management on Energy Saving Techniques in Interconnection Networks. Workshop Hipineb. 17 de February 2019,  Washington (EEUU).
  • G. Maglione-Mathey, J. Escudero-Sahuquillo, P. J. Garcia, F. J. Quiles and J. Duato, “Path2SL: Optimizing Head-of-Line Blocking Reduction in InfiniBand-Based Fat-Tree Networks,” 2019 IEEE Symposium on High-Performance Interconnects (HOTI), 2019, pp. 5-8, doi: 10.1109/HOTI.2019.00014.
  • Javier Cano-Cano, Francisco J. Andújar, Francisco J. Alfaro-Cortés, José L. Sánchez. VEF3 Traces: Towards a Complete Framework for Modelling Network Workloads for Exascale Systems. IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era (HiPINEB), p. 32-39, (2018).
  • Juan A. Villar, German Maglione-Mathey, Jesus Escudero-Sahuquillo, Pedro Javier Garcia, Francisco J. Alfaro-Cortés, José L. Sánchez and Francisco J. Quiles, “TopGen: A Library to Provide Simulation Tools with the Modeling of Interconnection Network Topologies”, 2018 International Conference on High Performance Computing Simulation (HPCS), 2018, pp. 452-459, https://doi.org/10.1109/HPCS.2018.00078