The final program of the Summer School will be published during May 2017. However, the confirmed speakers for the time being are the following:
- Jose Duato, Technical University of Valencia, Spain
- Eitan Zahavi, Mellanox Technologies, Israel
- Pedro J. García, University of Castilla-La Mancha, Spain
- Alain Cady, Atos/BULL, France
- Gaspar Mora, Intel Corp, Santa Clara, USA
- Holger Fröning, Ruprecht-Karls University of Heidelberg, Germany
- Bernard Metzler, IBM Zurich Research Laboratory, Zurich, Switzerland
Jose Duato is Professor in the Department of Computer Engineering (DISCA) at the Technical University of Valencia.His current research interests include interconnection networks, on-chip networks, and multicore and multiprocessor architectures. He published over 500 refereed papers. According to Google Scholar, his publications received more than 13,000 citations. He proposed a theory of deadlock-free adaptive routing that has been used in the design of the routing algorithms for the Cray T3E supercomputer, the on-chip router of the Alpha 21364 microprocessor, and the IBM BlueGene/L supercomputer. He also developed RECN, a scalable congestion management technique, and a very efficient routing algorithm for fat trees that has been incorporated into Sun Microsystem’s 3456-port InfiniBand Magnum switch. Prof. Duato led the Advanced Technology Group in the HyperTransport Consortium, and was the main contributor to the High Node Count HyperTransport Specification 1.0. He also led the development of rCUDA, which enables remote virtualized access to GP-GPU accelerators using a CUDA interface. Prof. Duato is the first author of the book “Interconnection Networks: An Engineering Approach”. He also served as a member of the editorial boards of IEEE Transactions on Parallel and Distributed Systems, IEEE Transactions on Computers, and IEEE Computer Architecture Letters. Prof. Duato was awarded with the National Research Prize in 2009 and the “Rey Jaime I” Prize in 2006.
Eitan Zahavi manages the Mellanox end-to-end performance architecture group which focuses on features that improve the overall system performance for both Ethernet and InfiniBand, lossy and lossless. We also study Optical Data Center networks. Example fields of research are Application performance, Congestion Control, Adaptive Routing, Tenants Isolation, and Topologies. The group employs large system simulation and lab experiments to validate our hypothesis and test new features implementations.
Pedro J. García is an Assistant Professor at UCLM. He has focused his research on developing strategies to improve several aspects of high-performance interconnection networks, especially congestion management schemes and routing algorithms, which have led to more than 40 publications in top-ranked journals and peer-reviewed conferences. He has guided one doctoral thesis and guides currently other three. He has been the coordinator of two research projects supported respectively by the Spanish Government and by the Government of Castilla-La Mancha, as well as the coordinator of two Research & Development Agreements. Besides, he has participated in other (more than 30) research projects, some of them supported by the European Commission. He has served as Organizer Committee member in several international workshops such as WHTRA, HiPINEB and WOPSSS.
Alain Cady is, from the very beginning of BuLL eXascale Interconnect (BXI) Fabric Management stack development, specifically in charge of the Topology Manager component design and implementation as part of the BXI Fabric Management solution: aims of this component is to provide other Fabric Management components initial in-memory fabric representation to work with and proper tooling to troubleshot clusters interconnect from hardware state to
cabling issues. This work involves close collaborations with several R&D teams such as Hardware & Firmware, Batch
Scheduler, Cluster Management, Factory and On-site Delivery. His professional activities well complete his HPC oriented education, as he also got previous experiment with Scientific Codes, notably using GPU as accelerator.
Gaspar Mora is currently part of the architecture team designing and developing next-generation Intel Omnipath products, where he is focusing on architecting a high-performance routing chip that will power future supercomputers. He received his PhD degree from the Universitat Politècnica de València (Spain) in 2009 and joined Intel Corporation in Santa Clara, California. Gaspar presently holds two granted US patents and has 5 patent applications.
Holger Fröning is an associate professor at the Department of Mathematics and Computer Science at the Ruprecht-Karls University of Heidelberg (Germany), leads the Computer Engineering Group at the Institute of Computer Engineering, and currently serves as deputy director of the same institute. His research interests include computer engineering, computer architecture and low-level software layers with a recent focus on performance and productivity for future and emerging technologies under hard power and energy constraints. In 2016, he spent 5 months at NVIDIA Research (Santa Clara, CA, US) as visiting scientist, sponsored by Bill Dally, with published results being acknowledged with an IPDPS best paper award. Early 2015 he was visiting professor at the Technical University of Graz (Austria) sponsored by Gernot Kubin. From 2008 to 2011 he was senior researcher at the Parallel Architectures Group at the Technical University of Valencia (Spain), led by Jose Duato. He has received his PhD and MSc degrees 2007 respectively 2001 from the University of Mannheim, Germany. His publications have been accepted at top-tier conferences, workshops and journals; in addition he contributed to several books. Parts of his research results have been commercialized. He regularly serves as program committee member for conferences and workshops (most recently SC, ICPP, ISC, CLUSTER and EuroPar), as reviewer for various journals, and leads the NVIDIA GPU Research and Education Center at Heidelberg University. His recent sponsors include BMBF, DFG, German Excellence Initiative, NVIDIA, SAP, Google, Xilinx, and Micron. For more information, please visit his website: http://www.ziti.uni-heidelberg.de/compeng
Bernard Metzler, PhD, graduated with a degree (Diplom) in Electrical Engineering from Humboldt University Berlin and a Ph.D. from Technical University Braunschweig, Germany, in 1999. He joined IBM Research – Zurich in 2000 as a Post-Doc and became a Research Staff Member in 2001. His main research interests are the design and implementation of flexible and highly efficient network communication stacks. He started at IBM working on communication software for the IBM Network Processor. Then he moved on to the specification and implementation of protocols and programming interfaces for Remote Direct Memory Access (RDMA). In that role he served as IBM representative and Co-Chair of the OpenGroup effort on RNICPI programming interface specification and contributed to the specification of an Internet RFC on the RDMAP protocol. Bernard joined the BlueGene Active Storage project, where he made significant contributions to its RDMA-based communication stack and the integration of non-volatile memory into a novel heterogenous memory hierarchy on BG/Q supercomputers. Bernard Metzler is the author of the open source ‘SoftiWarp’ RDMA implementation for Linux. His current focus is on “Whole Stack Optimization” — widening the scope for efficient communication including middleware such as the GPFS and HDFS file systems and Java-based communication.