{"id":178,"date":"2024-12-11T11:36:21","date_gmt":"2024-12-11T11:36:21","guid":{"rendered":"https:\/\/hipineb.i3a.info\/tetra-project\/?page_id=178"},"modified":"2024-12-11T12:18:10","modified_gmt":"2024-12-11T12:18:10","slug":"tecnicas-eficientes-para-tecnologias-de-red-avanzadas","status":"publish","type":"page","link":"https:\/\/hipineb.i3a.info\/tetra-project\/tecnicas-eficientes-para-tecnologias-de-red-avanzadas\/","title":{"rendered":"T\u00e9cnicas Eficientes para Tecnolog\u00edas de Red Avanzadas"},"content":{"rendered":"<p>En los \u00faltimos a\u00f1os, ha crecido enormemente la demanda, desde diversos \u00e1mbitos de la sociedad, de servicios TIC avanzados, tales como la supercomputaci\u00f3n o el proceso y an\u00e1lisis de conjuntos masivos de datos (Big-Data). Est\u00e1 previsto que esta demanda contin\u00fae aumentando hasta tal punto que, por ejemplo, se estima que en el a\u00f1o 2020 los supercomputadores deber\u00edan ofrecer una potencia 10 veces superior a la actual (alcanzando el nivel Exascale) para satisfacer las necesidades de sus usuarios. En general, en el futuro cercano los sistemas que soporten servicios TIC avanzados s\u00f3lo podr\u00e1n ofrecer las prestaciones demandadas aumentando considerablemente el n\u00famero de nodos de procesamiento y\/o almacenamiento que los componen. En consecuencia, las redes que interconecten dichos nodos deber\u00e1n ser mucho m\u00e1s eficientes que las de los sistemas actuales, para soportar necesidades de comunicaci\u00f3n mucho mayores, sin que se dispare su coste y su consumo energ\u00e9tico. Por ese motivo, tanto desde la industria como desde la academia se vienen realizando grandes esfuerzos en I+D orientados a acercar la eficiencia de las tecnolog\u00edas de red de interconexi\u00f3n a las exigencias de futuros sistemas. En este sentido, en este proyecto se propone desarrollar t\u00e9cnicas que, desde diversos aspectos del dise\u00f1o de la red, mejoren la eficiencia y el aprovechamiento de las tecnolog\u00edas punteras de redes de interconexi\u00f3n, de cara a facilitar la configuraci\u00f3n de infraestructuras de red capaces de interconectar eficientemente un mayor n\u00famero de nodos de computaci\u00f3n y\/o almacenamiento.<\/p>\n<h4><em><strong>Efficient Techniques for Advanced Interconnect Technologies<\/strong><\/em><\/h4>\n<p><em>In the last years, different sides of the society increasingly demand advanced ICT services such as supercomputing, or the processing and analysis of massive amounts of data (Big-Data). It is expected that this demand will continue growing so that, for instance, by the year 2020 supercomputers should offer a computational power ten times greater than the current one (reaching so the Exascale level), in order to satisfy the estimated needs of the users. In general, in the near future, the number of processing and storage nodes included in the systems supporting advanced ICT services will have to increase, in order to meet the expected performance requirements. Hence, the networks interconnecting these nodes will have to be much more efficient than current ones, in order to support much greater communication needs while preventing cost and energy consumption from skyrocketing. For these reasons, both the industry and the academia are devoting great R&amp;D efforts focused on bringing the efficiency of interconnect technologies closer to the requirements of future systems. In that sense, in this project we propose developing techniques that, from different aspects of the network, improve the efficiency and exploitation of leading interconnection-network technologies, in order to allow the configuration of network infrastructures able to efficiently interconnect a higher number of computing and storage nodes. The proposed research team consists of academic members with a wide experience in the field of interconnection networks, as well as experts from companies that are currently developing and producing high-performance interconnect technologies.<\/em><\/p>\n<h3><strong>Research Team<\/strong><\/h3>\n<ul>\n<li><strong>Francisco J. Alfaro <\/strong><em><a href=\"http:\/\/orcid.org\/0000-0002-4430-4482\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"http:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/04\/iD-icon.png\" alt=\"iD icon\" width=\"16\" height=\"16\" \/><\/a><\/em>\u00a0<a href=\"http:\/\/dblp.uni-trier.de\/pers\/hd\/a\/Alfaro:Francisco_J=\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"http:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/05\/dblp.icon_.18x18.png\" alt=\"dblp.icon.18x18\" width=\"18\" height=\"18\" \/><\/a> Full Professor at the Universidad de Castilla-La Mancha.<\/li>\n<li><strong>Pedro Javier Garc\u00eda <\/strong><a href=\"http:\/\/orcid.org\/0000-0002-7350-6067\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"http:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/04\/iD-icon.png\" alt=\"iD icon\" width=\"16\" height=\"16\" \/><\/a>\u00a0<a href=\"http:\/\/dblp.uni-trier.de\/pers\/hd\/g\/Garc=iacute=a:Pedro_Javier\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"http:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/05\/dblp.icon_.18x18.png\" alt=\"dblp.icon.18x18\" width=\"18\" height=\"18\" \/><\/a> Full Professor at the Universidad de Castilla-La Mancha.<\/li>\n<li><strong>Francisco Jos\u00e9 Quiles<\/strong><strong>\u00a0<a href=\"http:\/\/orcid.org\/0000-0002-8966-6225\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"http:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/04\/iD-icon.png\" alt=\"iD icon\" width=\"16\" height=\"16\" \/><\/a>\u00a0<a href=\"http:\/\/dblp.uni-trier.de\/pers\/hd\/q\/Quiles:Francisco_J=\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"http:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/05\/dblp.icon_.18x18.png\" alt=\"dblp.icon.18x18\" width=\"18\" height=\"18\" \/><\/a><\/strong>\u00a0Full Professor at the Universidad de Castilla-La Mancha.<\/li>\n<li><strong>Jos\u00e9 Luis S\u00e1nchez\u00a0<\/strong><strong><a href=\"http:\/\/orcid.org\/0000-0002-3498-9174\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"http:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/04\/iD-icon.png\" alt=\"iD icon\" width=\"16\" height=\"16\" \/><\/a>\u00a0<a href=\"http:\/\/dblp.uni-trier.de\/pers\/hd\/s\/S=aacute=nchez_0002:Jos=eacute=_L=\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"http:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/05\/dblp.icon_.18x18.png\" alt=\"dblp.icon.18x18\" width=\"18\" height=\"18\" \/><\/a> <\/strong>Full Professor at the Universidad de Castilla-La Mancha.<\/li>\n<li><strong>Jes\u00fas Escudero Sahuquillo\u00a0<\/strong><a href=\"http:\/\/orcid.org\/0000-0003-0835-8624\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"http:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/04\/iD-icon.png\" alt=\"iD icon\" width=\"16\" height=\"16\" \/><\/a>\u00a0<a href=\"http:\/\/dblp.uni-trier.de\/pers\/hd\/e\/Escudero=Sahuquillo:Jes=uacute=s\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"http:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/05\/dblp.icon_.18x18.png\" width=\"18\" height=\"18\" \/><\/a> Associate Profesor at the Universidad de Castilla-La Mancha.<\/li>\n<li><strong>Juan Jos\u00e9 Garc\u00eda-Castro Crespo<\/strong>. <strong><a href=\"https:\/\/dblp.org\/pid\/214\/1438.html\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone\" src=\"http:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/05\/dblp.icon_.18x18.png\" alt=\"dblp.icon.18x18\" width=\"18\" height=\"18\" \/><\/a><\/strong> Engineer at<a href=\"https:\/\/www.arm.com\/\"> ARM Ltd<\/a>.<\/li>\n<li><strong>Javier Cano Cano. <\/strong>Software Engineer at <a href=\"https:\/\/www.redhat.com\/\">Red Hat<\/a>.<\/li>\n<li><strong>Pedro Y\u00e9benes Segura<\/strong>\u00a0<a href=\"http:\/\/dblp.uni-trier.de\/pers\/hd\/y\/Yebenes:Pedro\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"http:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/05\/dblp.icon_.18x18.png\" alt=\"dblp.icon.18x18\" width=\"18\" height=\"18\" \/><\/a>Silicon Architecture Engineer at<a href=\"https:\/\/www.intel.com\"> Intel Corporation<\/a><\/li>\n<li><strong>Germ\u00e1n Maglione Mathey<\/strong> <a href=\"http:\/\/orcid.org\/0000-0002-4967-2268\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"http:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/04\/iD-icon.png\" alt=\"iD icon\" width=\"16\" height=\"16\" \/><\/a>\u00a0<a href=\"http:\/\/dblp.uni-trier.de\/pers\/hd\/m\/Mathey:German_Maglione\" target=\"_blank\" rel=\"noopener noreferrer\"><img decoding=\"async\" src=\"http:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/05\/dblp.icon_.18x18.png\" alt=\"dblp.icon.18x18\" width=\"18\" height=\"18\" \/><\/a>Senior Software Engineer at <a href=\"https:\/\/www.redhat.com\/\">Red Hat<\/a>.<\/li>\n<li><strong>Jose Manuel Rocher Gonz\u00e1lez. <a href=\"https:\/\/dblp.org\/pid\/207\/3465\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone\" src=\"http:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/05\/dblp.icon_.18x18.png\" alt=\"dblp.icon.18x18\" width=\"18\" height=\"18\" \/><\/a> <\/strong>Consultant at <a href=\"https:\/\/www.simula.no\/\">Simula Research Laboratory<\/a>.<\/li>\n<li><strong>Jos\u00e9 Duato Mar\u00edn. <span class=\"TextRun SCXW256202418 BCX4\" lang=\"ES-ES\" xml:lang=\"ES-ES\" data-contrast=\"auto\"><span class=\"NormalTextRun SCXW256202418 BCX4\"><a href=\"https:\/\/orcid.org\/0000-0002-7785-0607\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-393 size-full\" src=\"https:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/04\/iD-icon.png\" alt=\"\" width=\"16\" height=\"16\" \/><\/a><a href=\"https:\/\/dblp.org\/pid\/76\/2766.html\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-400 size-full\" src=\"https:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/05\/dblp.icon_.18x18.png\" alt=\"\" width=\"18\" height=\"18\" \/><\/a><\/span><\/span>\u00a0<\/strong> <a href=\"https:\/\/www.qsimov.com\/\" target=\"_blank\" rel=\"noopener\">Qsimov<\/a> CTO.<\/li>\n<li><strong><strong>Eitan Zahavi. <span class=\"TextRun SCXW256202418 BCX4\" lang=\"ES-ES\" xml:lang=\"ES-ES\" data-contrast=\"auto\"><span class=\"NormalTextRun SCXW256202418 BCX4\"><a href=\"https:\/\/dblp.org\/pid\/72\/7892.html\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-400 size-full\" src=\"https:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/05\/dblp.icon_.18x18.png\" alt=\"\" width=\"18\" height=\"18\" \/><\/a><\/span><\/span><\/strong><\/strong><span class=\"TextRun SCXW256202418 BCX4\" lang=\"ES-ES\" xml:lang=\"ES-ES\" data-contrast=\"auto\"><span class=\"NormalTextRun SCXW256202418 BCX4\">Distinguished Architect<\/span><\/span>at <a href=\"https:\/\/www.nvidia.com\/\" target=\"_blank\" rel=\"noopener\">Nvidia Corporation.<\/a><\/li>\n<li><strong>Gaspar Mora Porta<\/strong>. <strong><span class=\"TextRun SCXW256202418 BCX4\" lang=\"ES-ES\" xml:lang=\"ES-ES\" data-contrast=\"auto\"><span class=\"NormalTextRun SCXW256202418 BCX4\"><a href=\"https:\/\/orcid.org\/0000-0002-7785-0607\" target=\"_blank\" rel=\"noopener\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-393 size-full\" src=\"https:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/04\/iD-icon.png\" alt=\"\" width=\"16\" height=\"16\" \/><\/a><a href=\"https:\/\/dblp.org\/pid\/04\/447.html\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-400 size-full\" src=\"https:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/05\/dblp.icon_.18x18.png\" alt=\"\" width=\"18\" height=\"18\" \/>\u00a0<\/a><\/span><\/span><\/strong>Senior Architect at <a href=\"https:\/\/www.nvidia.com\/\" target=\"_blank\" rel=\"noopener\">Nvidia Corporation.<\/a><\/li>\n<li><strong>Torsten Hoefler <span class=\"TextRun SCXW256202418 BCX4\" lang=\"ES-ES\" xml:lang=\"ES-ES\" data-contrast=\"auto\"><span class=\"NormalTextRun SCXW256202418 BCX4\"><a href=\"https:\/\/dblp.org\/pid\/16\/3869.html\" target=\"_blank\" rel=\"noopener noreferrer\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-400 size-full\" src=\"https:\/\/www.i3a.uclm.es\/raap\/wp-content\/uploads\/2016\/05\/dblp.icon_.18x18.png\" alt=\"\" width=\"18\" height=\"18\" \/><\/a><\/span><\/span><\/strong><span class=\"TextRun SCXW256202418 BCX4\" lang=\"ES-ES\" xml:lang=\"ES-ES\" data-contrast=\"auto\"><span class=\"NormalTextRun SCXW256202418 BCX4\">Full Professor at the <a href=\"https:\/\/ethz.ch\/\">ETH Z\u00fcrich<\/a>.<\/span><\/span><\/li>\n<\/ul>\n<h3><strong>PhD Thesis<\/strong><\/h3>\n<ul>\n<li><strong>New Queuing Schemes to Improve the Efficiency of Hybrid and Hierarchical High-Performance Interconnection Network Topologies<br \/>\n<\/strong>Student: Pedro Y\u00e9benes Segura. Advisors: Jes\u00fas Escudero Sahuquillo y Pedro Javier Garcia Garc\u00eda. Reading date: 05\/11\/2018.<\/li>\n<li><strong>Habilitaci\u00f3n de calidad de servicio en arquitecturas de switch jer\u00e1rquico<br \/>\n<\/strong>Student: Javier Cano Cano. Advisors: Francisco Jos\u00e9 Alfaro Cort\u00e9s y Francisco Jos\u00e9 And\u00fajar Mu\u00f1oz.Reading date: 07\/10\/2021.<\/li>\n<li><strong>Efficient routing, job-isolation and congestion control techniques in commercial interconnection networks<br \/>\n<\/strong>Student:German Horacio Maglione Mathey. Advisors: Jes\u00fas Escudero Sahuquillo y Pedro Javier Garcia Garc\u00eda. Planned reading date: 18\/10\/2021.<\/li>\n<li><strong>Upstream Progressive Network Reconfiguration Schemes for High Performance Networks<br \/>\n<\/strong>Student: Juan Jos\u00e9 Garc\u00eda-Castro Crespo. Advisors: Francisco Jos\u00e9 Alfaro Cort\u00e9s, Jos\u00e9 Luis S\u00e1nchez Garc\u00eda y Jos\u00e9 Flich Cardo. Planned reading date: \/11\/2021.<\/li>\n<\/ul>\n<h3><strong>Journals<\/strong><\/h3>\n<ul>\n<li><span class=\"wpmauthors\">Javier Cano-Cano, Francisco J. And\u00fajar, Francisco J. Alfaro-Cort\u00e9s, Jos\u00e9 L. S\u00e1nchez.\u00a0<\/span><span class=\"wpmtitle\">Enabling Quality of Service Provision in Omni-Path Switches.\u00a0<\/span><span class=\"wpmoutlet\">Computational and Mathematical Methods<\/span>, <span class=\"wpmpages\">p. e1147<\/span>, <span class=\"wpmpublisher\">John Wiley &amp; Sons, Ltd<\/span>, (2021).\u00a0<span class=\"wpmurl\"><a href=\"https:\/\/doi.org\/10.1002\/CMM4.1147\" target=\"_blank\" rel=\"noopener\"><span class=\"wpmurldoi:10.1002\/CMM4.1147\">doi:10.1002\/CMM4.1147<\/span><\/a><\/span><\/li>\n<li>\n<p class=\"wpmref\"><span class=\"wpmauthors\">Cristina Olmedilla, Jesus Escudero-Sahuquillo, Pedro Javier Garcia-Garcia, Francisco Alfaro-Cortes, Jose L. Sanchez, Francisco J. Quiles, Wenhao Sun, Xiang Yu, Yonghui Xu, Jose Duato.\u00a0<\/span><span class=\"wpmtitle\">DVL-Lossy: Isolating congesting flows to optimize packet dropping in lossy data-center networks.\u00a0<\/span><span class=\"wpmoutlet\">IEEE Micro<\/span> <span class=\"wpmvolume\">41<\/span><span class=\"wpmissue\">(1)<\/span>, <span class=\"wpmpages\">p. 37-44<\/span>, <span class=\"wpmpublisher\">IEEE Computer Society (2021)<\/span>, <span class=\"wpmurl\"><a href=\"https:\/\/doi.org\/10.1109\/MM.2020.3042263\" target=\"_blank\" rel=\"noopener\"><span class=\"wpmurldoi:10.1109\/MM.2020.3042263\">doi:10.1109\/MM.2020.3042263<\/span><\/a><\/span><\/p>\n<\/li>\n<li><span class=\"wpmauthors\">Javier Cano-Cano, Francisco J. And\u00fajar, Jes\u00fas Escudero-Sahuquillo, Francisco J. Alfaro-Cort\u00e9s, Jos\u00e9 L. S\u00e1nchez.\u00a0<\/span><span class=\"wpmtitle\">A methodology to enable QoS provision on InfiniBand hardware.\u00a0<\/span><span class=\"wpmoutlet\">The Journal of Supercomputing 2021 77:9<\/span> <span class=\"wpmvolume\">77<\/span><span class=\"wpmissue\">(9)<\/span>, <span class=\"wpmpages\">p. 9934-9946<\/span>, <span class=\"wpmpublisher\">Springer\u00a0<\/span><span class=\"wpmyear\">(2021).<\/span>\u00a0<span class=\"wpmurl\"><a href=\"https:\/\/link.springer.com\/article\/10.1007\/s11227-021-03667-x\" target=\"_blank\" rel=\"noopener\"><span class=\"wpmurlurl\">url<\/span><\/a><\/span>, <span class=\"wpmurl\"><a href=\"https:\/\/doi.org\/10.1007\/S11227-021-03667-X\" target=\"_blank\" rel=\"noopener\"><span class=\"wpmurldoi:10.1007\/S11227-021-03667-X\">doi:10.1007\/S11227-021-03667-X<\/span><\/a><\/span><\/li>\n<li><span class=\"wpmauthors\">Javier Cano-Cano, Francisco J. And\u00fajar, Francisco J. Alfaro-Cort\u00e9s, Jos\u00e9 L. S\u00e1nchez.\u00a0<\/span><span class=\"wpmtitle\">QoS provision in hierarchical and non-hierarchical switch architectures.\u00a0<\/span><span class=\"wpmoutlet\">Journal of Parallel and Distributed Computing<\/span> <span class=\"wpmvolume\">148<\/span>, <span class=\"wpmpages\">p. 138-150<\/span>, <span class=\"wpmpublisher\">Academic Press (2021). <\/span><span class=\"wpmurl\"><a href=\"https:\/\/doi.org\/10.1016\/J.JPDC.2020.10.009\" target=\"_blank\" rel=\"noopener\"><span class=\"wpmurldoi:10.1016\/J.JPDC.2020.10.009\">doi:10.1016\/J.JPDC.2020.10.009<\/span><\/a><\/span><\/li>\n<li>\n<p class=\"wpmref\"><span class=\"wpmauthors\">Jose Rocher-Gonzalez, Jesus Escudero-Sahuquillo, Pedro J. Garc\u00eda, Francisco J. Quiles, Gaspar Mora<\/span><span class=\"wpmyear\">.\u00a0<\/span><span class=\"wpmtitle\">Towards an efficient combination of adaptive routing and queuing schemes in Fat-Tree topologies.\u00a0<\/span><span class=\"wpmoutlet\">Journal of Parallel and Distributed Computing<\/span> <span class=\"wpmvolume\">147<\/span>, <span class=\"wpmpages\">p. 46-63<\/span>, <span class=\"wpmpublisher\">Academic Press<\/span>\u00a0<span class=\"wpmyear\">(2021).\u00a0<\/span><span class=\"wpmurl\"><a href=\"https:\/\/doi.org\/10.1016\/J.JPDC.2020.07.009\" target=\"_blank\" rel=\"noopener\"><span class=\"wpmurldoi:10.1016\/J.JPDC.2020.07.009\">doi:10.1016\/J.JPDC.2020.07.009<\/span><\/a><\/span><\/p>\n<\/li>\n<li>\n<p class=\"wpmref\"><span class=\"wpmauthors\">German Maglione-Mathey, Jesus Escudero-Sahuquillo, Pedro Javier Garcia, Francisco J. Quiles, Eitan Zahavi.<\/span>\u00a0Leveraging InfiniBand controller to configure deadlock-free routing engines for Dragonflies.\u00a0<span class=\"wpmoutlet\">Journal of Parallel and Distributed Computing<\/span> <span class=\"wpmvolume\">147<\/span>, <span class=\"wpmpages\">p. 16-33<\/span>, <span class=\"wpmpublisher\">Academic Press. <span class=\"wpmyear\">(2021)\u00a0<\/span><\/span><span class=\"wpmurl\"><a href=\"https:\/\/doi.org\/10.1016\/J.JPDC.2020.07.010\" target=\"_blank\" rel=\"noopener\"><span class=\"wpmurldoi:10.1016\/J.JPDC.2020.07.010\">doi:10.1016\/J.JPDC.2020.07.010<\/span><\/a><\/span><\/p>\n<\/li>\n<li><span class=\"wpmauthors\">Juan-Jos\u00e9 Crespo, Jos\u00e9 L. S\u00e1nchez, Francisco J. Alfaro-Cort\u00e9s, Jos\u00e9 Flich, Jos\u00e9 Duato.\u00a0<\/span><span class=\"wpmtitle\">UPR: deadlock-free dynamic network reconfiguration by exploiting channel dependency graph compatibility.\u00a0<\/span><span class=\"wpmoutlet\">The Journal of Supercomputing 2021<\/span>, <span class=\"wpmpages\">p. 1-31<\/span>, <span class=\"wpmpublisher\">Springer\u00a0<\/span><span class=\"wpmyear\">(2021)<\/span><span class=\"wpmurl\"> <a href=\"https:\/\/doi.org\/10.1007\/S11227-021-03791-8\" target=\"_blank\" rel=\"noopener\"><span class=\"wpmurldoi:10.1007\/S11227-021-03791-8\">doi:10.1007\/S11227-021-03791-8<\/span><\/a><\/span><\/li>\n<li><span class=\"wpmauthors\">German Maglione-Mathey, Jesus Escudero-Sahuquillo, Pedro Javier Garcia, Francisco J. Quiles, Jose Duato.\u00a0<\/span><span class=\"wpmtitle\">Path2SL: Leveraging InfiniBand resources to reduce head-of-line blocking in fat trees.\u00a0<\/span><span class=\"wpmoutlet\">IEEE Micro<\/span> <span class=\"wpmvolume\">40<\/span><span class=\"wpmissue\">(1)<\/span>, <span class=\"wpmpages\">p. 8-14<\/span>, <span class=\"wpmpublisher\">IEEE Computer Society<\/span>, (2020), <span class=\"wpmurl\"><a href=\"https:\/\/doi.org\/10.1109\/MM.2019.2949280\" target=\"_blank\" rel=\"noopener\"><span class=\"wpmurldoi:10.1109\/MM.2019.2949280\">doi:10.1109\/MM.2019.2949280<\/span><\/a><\/span><\/li>\n<li><span class=\"wpmauthors\">John Gliksberg, Antoine Capra, Alexandre Louvet, Pedro Javier Garcia, Devan Sohier.\u00a0<\/span><span class=\"wpmtitle\">High-quality fault resiliency in fat trees<\/span><br \/>\n<span class=\"wpmoutlet\">IEEE Micro<\/span> <span class=\"wpmvolume\">40<\/span><span class=\"wpmissue\">(1)<\/span>, <span class=\"wpmpages\">p. 44-49<\/span>, <span class=\"wpmpublisher\">IEEE Computer Society<\/span>, (2020), <span class=\"wpmurl\"><a href=\"https:\/\/doi.org\/10.1109\/MM.2019.2949978\" target=\"_blank\" rel=\"noopener\"><span class=\"wpmurldoi:10.1109\/MM.2019.2949978\">doi:10.1109\/MM.2019.2949978<\/span><\/a><\/span><\/li>\n<li><span class=\"wpmauthors\">Francisco J. And\u00fajar, Juan A. Villar, Jos\u00e9 L. S\u00e1nchez, Francisco J. Alfaro, Jos\u00e9 Duato, Holger Fr\u00f6ning.\u00a0<\/span><span class=\"wpmtitle\">Constructing virtual 5-dimensional tori out of lower-dimensional network cards.\u00a0<\/span><span class=\"wpmoutlet\">Concurrency Computation<\/span> <span class=\"wpmvolume\">31<\/span><span class=\"wpmissue\">(2)<\/span>, <span class=\"wpmpages\">p. e4361<\/span>, <span class=\"wpmpublisher\">John Wiley and Sons Ltd\u00a0<\/span><span class=\"wpmyear\">(2019).<\/span><span class=\"wpmurl\"> <a href=\"https:\/\/doi.org\/10.1002\/cpe.4361\" target=\"_blank\" rel=\"noopener\"><span class=\"wpmurldoi:10.1002\/cpe.4361\">doi:10.1002\/cpe.4361<\/span><\/a><\/span><\/li>\n<li><span class=\"wpmauthors\">Javier Cano-Cano, Francisco J. And\u00fajar, Francisco J. Alfaro, Jos\u00e9 L. S\u00e1nchez<\/span><span class=\"wpmyear\">.\u00a0<\/span><span class=\"wpmtitle\">Speeding up exascale interconnection network simulations with the VEF3 trace framework.\u00a0<\/span><span class=\"wpmoutlet\">Journal of Parallel and Distributed Computing<\/span> <span class=\"wpmvolume\">133<\/span>, <span class=\"wpmpages\">p. 124-135<\/span>, <span class=\"wpmpublisher\">Academic Press Inc. (2019).<\/span>\u00a0<span class=\"wpmurl\"><a href=\"https:\/\/doi.org\/10.1016\/j.jpdc.2019.06.013\" target=\"_blank\" rel=\"noopener\"><span class=\"wpmurldoi:10.1016\/j.jpdc.2019.06.013\">doi:10.1016\/j.jpdc.2019.06.013<\/span><\/a><\/span><\/li>\n<li><span class=\"wpmauthors\">Juan Jose Crespo, Jos\u00e9 L. S\u00e1nchez, Francisco J. Alfaro-Cort\u00e9s.\u00a0<\/span><span class=\"wpmtitle\">Silicon photonic networks: Signal loss and power challenges.\u00a0<\/span><span class=\"wpmoutlet\">Concurrency Computation <\/span><span class=\"wpmvolume\">31<\/span><span class=\"wpmissue\">(21)<\/span>, <span class=\"wpmpages\">p. 1-14 (2019),<\/span>\u00a0<span class=\"wpmurl\"><a href=\"https:\/\/doi.org\/10.1002\/cpe.4777\" target=\"_blank\" rel=\"noopener\"><span class=\"wpmurldoi:10.1002\/cpe.4777\">doi:10.1002\/cpe.4777<\/span><\/a><\/span><\/li>\n<li><span class=\"wpmauthors\">Pedro Yebenes, Jose Rocher-Gonzalez, Jesus Escudero-Sahuquillo, Pedro Javier Garcia, Francisco J. Alfaro, Francisco J. Quiles, Crisp\u00edn G\u00f3mez, Jose Duato.\u00a0<\/span><span class=\"wpmtitle\">Combining Source-adaptive and Oblivious Routing with Congestion Control in High-performance Interconnects using Hybrid and Direct Topologies.\u00a0<\/span><span class=\"wpmoutlet\">ACM Transactions on Architecture and Code Optimization<\/span> <span class=\"wpmvolume\">16<\/span><span class=\"wpmissue\">(2)<\/span>, <span class=\"wpmpages\">p. 1-26<\/span>, <span class=\"wpmpublisher\">Association for Computing Machinery (2019).<\/span>\u00a0<span class=\"wpmurl\"><a href=\"https:\/\/doi.org\/10.1145\/3319805\" target=\"_blank\" rel=\"noopener\"><span class=\"wpmurldoi:10.1145\/3319805\">doi:10.1145\/3319805<\/span><\/a><\/span><\/li>\n<li>Escudero, P.J. Garc\u00eda, F.J. Quiles, J. Duato, G. Maglione. Feasible enhancements to congestion control in InfiniBand-based networks. Journal of Parallel and Distributed Computing (2018). <span class=\"wpmurl\"><a href=\"https:\/\/doi.org\/10.1016\/j.jpdc.2017.09.008\" target=\"_blank\" rel=\"noopener\"><span class=\"wpmurldoi:10.1016\/j.jpdc.2017.09.008\">doi:10.1016\/j.jpdc.2017.09.008<\/span><\/a><\/span><\/li>\n<li>Maglione, P. Y\u00e9benes, J. Escudero, P.J. Garc\u00eda, F.J. Quiles, E. Zahavi. Scalable Deadlock-free Deterministic Minimal-Path Routing Engine for InfiniBand-Based Dragonfly Networks. IEEE Transactions on Parallel and Distributed Systems (2018) <span class=\"wpmurl\"><a href=\"https:\/\/doi.org\/10.1109\/TPDS.2017.2742503\" target=\"_blank\" rel=\"noopener\"><span class=\"wpmurldoi:10.1109\/TPDS.2017.2742503\">doi:10.1109\/TPDS.2017.2742503<\/span><\/a><\/span><\/li>\n<\/ul>\n<h3><strong>International Conferences<\/strong><\/h3>\n<ul>\n<li><span class=\"gmail-this-person\">JM. Rocher, J. Escudero, P.J. Garc\u00eda, F.J. Quiles, G. Mora.\u00a0<\/span><span class=\"gmail-title\">Efficient Congestion Management for High-Speed Interconnects using Adaptive Routing.<\/span> <a href=\"https:\/\/dblp.org\/db\/conf\/ccgrid\/ccgrid2019.html#Rocher-Gonzalez19\">CCGRID 2019<\/a>: 221-230<\/li>\n<li>Crespo, J. J., Maglione-Mathey, G., Sanchez, J. L., Alfaro-Cortes, F. J., Escudero-Sahuquillo, J., Garcia, P. J., &amp; Quiles, F. J. (2019, July). Methodology for Decoupled Simulation of SystemVerilog HDL Designs. In 2019 International Conference on High Performance Computing &amp; Simulation (HPCS) (pp. 741-746). IEEE. <a href=\"https:\/\/doi.org\/10.1109\/hpcs48598.2019.9188056\">https:\/\/doi.org\/10.1109\/hpcs48598.2019.9188056<\/a><\/li>\n<li>J. Gliksberg, A. Capra, A. Louvet, P. J. Garcia, and D. Sohier: \u201cDmodc: High-Quality Fault-Resiliency in Fat-Tree Networks\u201d. 26th Simposium on High-Performance Interconnects (HOTI), \u00a0August\u00a02019,\u00a0Santa Clara (EEUU).<\/li>\n<li>Luis Gonzalez-Naharro, Jes\u00fas Escudero-Sahuquillo, Pedro Javier Garcia, Francisco J. Quiles, Jose Duato, Wenhao Sun, Li Shen, Xiang Yu and Hewen Zheng. Efficient Dynamic Isolation of Congestion in Lossless DataCenter Networks. ACM SIGCOMM 2019 Workshop on Networking for Emerging Applications and Technologies (NEAT), August 2019, Beijing, China.<\/li>\n<li>Luis Gonzalez-Naharro,\u00a0Jes\u00fas Escudero-Sahuquillo,\u00a0Pedro Javier Garc\u00eda,\u00a0Francisco Jos\u00e9 Quiles Flor,\u00a0Jos\u00e9 Duato,\u00a0Wenhao Sun,\u00a0Li Shen,\u00a0Xiang Yu,\u00a0Hewen Zheng: Modeling Traffic Workloads in Data-center Network Simulation Tools. HPCS 2019, Dublin, Ireland.<\/li>\n<li>Felix Zahn, Pedro Yebenes, Jesus Escudero-Sahuquillo, Pedro Javier Garcia and Holger Froening. Effects of Congestion Management on Energy Saving Techniques in Interconnection Networks. Workshop Hipineb. 17 de\u00a0February\u00a02019, \u00a0Washington (EEUU).<\/li>\n<li>G. Maglione-Mathey, J. Escudero-Sahuquillo, P. J. Garcia, F. J. Quiles and J. Duato, \u201cPath2SL: Optimizing Head-of-Line Blocking Reduction in InfiniBand-Based Fat-Tree Networks,\u201d 2019 IEEE Symposium on High-Performance Interconnects (HOTI), 2019, pp. 5-8, doi: 10.1109\/HOTI.2019.00014.<\/li>\n<li>Javier Cano-Cano, Francisco J. And\u00fajar, Francisco J. Alfaro-Cort\u00e9s, Jos\u00e9 L. S\u00e1nchez. VEF3 Traces: Towards a Complete Framework for Modelling Network Workloads for Exascale Systems. IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era (HiPINEB), p. 32-39, (2018).<\/li>\n<li>Juan A. Villar, German Maglione-Mathey, Jesus Escudero-Sahuquillo, Pedro Javier Garcia, Francisco J. Alfaro-Cort\u00e9s, Jos\u00e9 L. S\u00c3\u00a1nchez and Francisco J. Quiles, \u201cTopGen: A Library to Provide Simulation Tools with the Modeling of Interconnection Network Topologies\u201d, 2018 International Conference on High Performance Computing Simulation (HPCS), 2018, pp. 452-459, <a href=\"https:\/\/doi.org\/10.1109\/HPCS.2018.00078\">https:\/\/doi.org\/10.1109\/HPCS.2018.00078<\/a><\/li>\n<\/ul>\n<p>&nbsp;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>En los \u00faltimos a\u00f1os, ha crecido enormemente la demanda, desde diversos \u00e1mbitos de la sociedad, de servicios TIC avanzados, tales como la supercomputaci\u00f3n o el proceso y an\u00e1lisis de conjuntos &#8230;<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"footnotes":""},"class_list":["post-178","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/hipineb.i3a.info\/tetra-project\/wp-json\/wp\/v2\/pages\/178","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hipineb.i3a.info\/tetra-project\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/hipineb.i3a.info\/tetra-project\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/hipineb.i3a.info\/tetra-project\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/hipineb.i3a.info\/tetra-project\/wp-json\/wp\/v2\/comments?post=178"}],"version-history":[{"count":3,"href":"https:\/\/hipineb.i3a.info\/tetra-project\/wp-json\/wp\/v2\/pages\/178\/revisions"}],"predecessor-version":[{"id":181,"href":"https:\/\/hipineb.i3a.info\/tetra-project\/wp-json\/wp\/v2\/pages\/178\/revisions\/181"}],"wp:attachment":[{"href":"https:\/\/hipineb.i3a.info\/tetra-project\/wp-json\/wp\/v2\/media?parent=178"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}