{"id":89,"date":"2017-01-04T00:47:27","date_gmt":"2017-01-04T00:47:27","guid":{"rendered":"http:\/\/hipineb.i3a.info\/hipineb2017\/?page_id=89"},"modified":"2017-05-04T12:31:49","modified_gmt":"2017-05-04T12:31:49","slug":"program","status":"publish","type":"page","link":"https:\/\/hipineb.i3a.info\/hipineb2017\/program\/","title":{"rendered":"Program"},"content":{"rendered":"<p><a id=\"#top\"><\/a>The workshop will take place in\u00a0<a href=\"http:\/\/hpca2017.org\/venue\/\">Hilton Austin,\u00a0500 E 4th St,\u00a0Austin, TX 78701<\/a>. The room for the HiPINEB workshop will be <span style=\"color: #ff0000;\"><strong>400\/402<\/strong><\/span>.\u00a0Speakers of Technical Sessions have 20 minutes for their presentations, plus 2 minutes for questions from the audience.<\/p>\n<p><strong>7:30 &#8211; 8:30am &#8211; Breakfast (616AB)<\/strong><\/p>\n<p><strong>8:30 &#8211; 8:40am &#8211; Opening\u00a0<strong><a href=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/05\/presentation-speech.pdf\"><img decoding=\"async\" class=\"alignnone wp-image-158\" src=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/01\/pdf-icon.png\" alt=\"pdf-icon\" width=\"30\" height=\"30\" \/><\/a><\/strong><\/strong><br \/>\n<em>Pedro Javier Garcia, University of Castilla-La Mancha, Spain<\/em><br \/>\n<em> Jesus Escudero-Sahuquillo, University of Castilla-La Mancha, Spain<\/em><\/p>\n<p><strong>8:40 &#8211; 10:00am &#8211; Keynote<\/strong><br \/>\n<em>Chairman: Francisco J. Quiles, University of Castilla-La Mancha, Spain<\/em><\/p>\n<p><strong><a href=\"#dally\">Issues in the Design of an Exascale Network<\/a>\u00a0<strong><strong><a href=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/05\/slides_dally.pdf\"><img decoding=\"async\" class=\"alignnone wp-image-158\" src=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/01\/pdf-icon.png\" alt=\"pdf-icon\" width=\"30\" height=\"30\" \/><\/a><\/strong><\/strong><br \/>\n<\/strong><em>Bill Dally, Chief Scientist and SVP of Research in NVIDIA, and Stanford Professor<\/em><\/p>\n<p><strong>10:00 &#8211; 10:30am &#8211; Break (room 616AB)<\/strong><\/p>\n<p><strong>10:30 &#8211; 12:00am &#8211; Panel<\/strong><\/p>\n<p><strong><a href=\"#panel\">Massive-storage Networks vs Intensive-computing Networks<\/a>\u00a0<strong><a href=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/05\/panel_intro.pdf\"><img decoding=\"async\" class=\"alignnone wp-image-158\" src=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/01\/pdf-icon.png\" alt=\"pdf-icon\" width=\"30\" height=\"30\" \/><\/a><\/strong><br \/>\n<\/strong><em>Moderator:\u00a0John Kim, HP Labs \/ KAIST, South-Korea<\/em><\/p>\n<p>Panelists:<\/p>\n<ul>\n<li>Dave Mayhew, San Diego University, USA\u00a0<strong><strong><a href=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/05\/panel_dave.pdf\"><img decoding=\"async\" class=\"alignnone wp-image-158\" src=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/01\/pdf-icon.png\" alt=\"pdf-icon\" width=\"30\" height=\"30\" \/><\/a><\/strong><\/strong><\/li>\n<li>Bill Dally, NVIDIA and Stanford University, USA\u00a0<strong><strong><a href=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/05\/panel_dally.pdf\"><img decoding=\"async\" class=\"alignnone wp-image-158\" src=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/01\/pdf-icon.png\" alt=\"pdf-icon\" width=\"30\" height=\"30\" \/><\/a><\/strong><\/strong><\/li>\n<li>Torsten Hoefler, ETH Zurich, Switzerland\u00a0<strong><strong><a href=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/05\/panel_torsten.pptx\"><img decoding=\"async\" class=\"alignnone wp-image-158\" src=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/01\/pdf-icon.png\" alt=\"pdf-icon\" width=\"30\" height=\"30\" \/><\/a><\/strong><\/strong><\/li>\n<\/ul>\n<p><strong>12:00 &#8211; 1:30pm &#8211; Lunch\u00a0<\/strong><\/p>\n<p><strong>1:30 &#8211; 3:00pm\u00a0&#8211; Technical Sessions<br \/>\n<\/strong><em>Chairman: Michihiro Koibuchi, National Institute of Informatics, Japan<\/em><\/p>\n<ul>\n<li><strong><a href=\"#shpiner\">Dragonfly+: Low Cost Topology for Scaling Data Centers<\/a>\u00a0<strong><a href=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/05\/slides_alex.pdf\"><img decoding=\"async\" class=\"alignnone wp-image-158\" src=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/01\/pdf-icon.png\" alt=\"pdf-icon\" width=\"30\" height=\"30\" \/><\/a><\/strong><\/strong><br \/>\n<em>Alexander Shpiner, Zachy Haramaty, Saar Eliad, Vladimir Zdornov, Barak Gafni and Eitan Zahavi (Mellanox Technologies, Israel)<\/em><\/li>\n<li><strong><a href=\"#andujar\">A case study on implementing virtual 5D torus networks using network components of lower dimensionality<\/a>\u00a0<strong><a href=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/05\/slides_fran.pdf\"><img decoding=\"async\" class=\"alignnone wp-image-158\" src=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/01\/pdf-icon.png\" alt=\"pdf-icon\" width=\"30\" height=\"30\" \/><\/a><\/strong><\/strong><br \/>\n<em>Francisco Andujar-Mu\u00f1oz, Juan A. Villar, Jose L. Sanchez, Francisco Alfaro and Holger Fr\u00f6ning (University of Castilla-La Mancha, Spain, and Ruprecht-Karls University of Heidelberg, Germany)<\/em><\/li>\n<li><strong><a href=\"#belka\">New link arrangements for Dragonfly networks<\/a>\u00a0<strong><a href=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/05\/slides_bunde.pdf\"><img decoding=\"async\" class=\"alignnone wp-image-158\" src=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/01\/pdf-icon.png\" alt=\"pdf-icon\" width=\"30\" height=\"30\" \/><\/a><\/strong><\/strong><br \/>\n<em>Madison Belka, Myra Doubet, Sofia Meyers, Rosemary Momoh, David Rincon-Cruz and David Bunde (Knox College, and\u00a0Columbia University, USA)<\/em><\/li>\n<li><strong><a href=\"#yebenes\">An Effective Queuing Scheme to Provide Slim Fly topologies with HoL Blocking Reduction and Deadlock Freedom for Minimal-Path Routing<\/a>\u00a0<strong><a href=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/05\/slides_yebenes.pdf\"><img decoding=\"async\" class=\"alignnone wp-image-158\" src=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/01\/pdf-icon.png\" alt=\"pdf-icon\" width=\"30\" height=\"30\" \/><\/a><\/strong><\/strong><br \/>\n<em>Pedro Yebenes Segura, Jesus Escudero-Sahuquillo, Pedro Javier Garcia, Francisco J. Quiles and Torsten Hoefler (University of Castilla-La Mancha, Spain, and ETH Zurich, Switzerland)<\/em><\/li>\n<\/ul>\n<p><strong>3:00 &#8211; 3:30pm\u00a0&#8211; Break (room 616AB)<\/strong><\/p>\n<p><strong>3:30 &#8211; 4:55pm\u00a0&#8211; Technical Sessions<\/strong><br \/>\n<em>Chairman:\u00a0Jesus Escudero-Sahuquillo<\/em><\/p>\n<ul>\n<li><strong><a href=\"#zahn\">Early Experiences with Saving Energy in Direct Interconnection Networks<\/a>\u00a0<strong><a href=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/05\/slides_felix.pdf\"><img decoding=\"async\" class=\"alignnone wp-image-158\" src=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/01\/pdf-icon.png\" alt=\"pdf-icon\" width=\"30\" height=\"30\" \/><\/a><\/strong><\/strong><br \/>\n<em>Felix Zahn, Steffen Lammel and Holger Fr\u00f6ning (<em>Ruprecht-Karls University of Heidelberg, Germany)<\/em><\/em><\/li>\n<li><strong><a href=\"#benito\">Extending commodity OpenFlow switches for large-scale HPC deployments<\/a>\u00a0<strong><a href=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/05\/slides_benito.pdf\"><img decoding=\"async\" class=\"alignnone wp-image-158\" src=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/01\/pdf-icon.png\" alt=\"pdf-icon\" width=\"30\" height=\"30\" \/><\/a><\/strong><\/strong><br \/>\n<em>Mariano Benito, Enrique Vallejo, Ram\u00f3n Beivide and Cruz Izu (University of Cantabria, Spain, and\u00a0The University of Adelaide, Australia)<\/em><\/li>\n<li><strong><a href=\"#perotin\">Isolating jobs for security on high-performance fabrics<\/a>\u00a0<strong><a href=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/05\/slides_perotin.pdf\"><img decoding=\"async\" class=\"alignnone wp-image-158\" src=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/01\/pdf-icon.png\" alt=\"pdf-icon\" width=\"30\" height=\"30\" \/><\/a><\/strong><\/strong><br \/>\n<em>Matthieu P\u00e9rotin and Tom Cornebize (Atos, France, and\u00a0ENS Lyon, France)<\/em><\/li>\n<li><strong><a href=\"#shim\">Knapp: A Packet Processing Framework for Manycore Accelerators<\/a>\u00a0<strong><a href=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/05\/slides_moon.pdf\"><img decoding=\"async\" class=\"alignnone wp-image-158\" src=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/01\/pdf-icon.png\" alt=\"pdf-icon\" width=\"30\" height=\"30\" \/><\/a><\/strong><\/strong><br \/>\n<em>Junhyun Shim, Joongi Kim, Keunhong Lee and Sue Moon (SAP Labs Korea,\u00a0Lablup Inc. and KAIST, South Korea)<\/em><\/li>\n<\/ul>\n<p><strong>4:55 &#8211; 5:00pm &#8211; Closing<\/strong><\/p>\n<hr \/>\n<p>&nbsp;<\/p>\n<h3><strong>Detailed Program<\/strong><\/h3>\n<h4><strong><a id=\"dally\"><\/a>Keynote<\/strong><\/h4>\n<p><em><strong>Issues in the Design of an Exascale Network<br \/>\n<\/strong><em>Bill Dally, Chief Scientist and SVP of Research in NVIDIA, and Stanford Professor<\/em><strong><br \/>\n<\/strong><\/em><\/p>\n<p><a href=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2016\/11\/Bill_Dally.jpg\"><img decoding=\"async\" class=\"alignleft wp-image-57\" src=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2016\/11\/Bill_Dally.jpg\" alt=\"bill_dally\" width=\"173\" height=\"235\" \/><\/a><\/p>\n<p>Bill Dally joined NVIDIA in January 2009 as chief scientist, after spending 12 years at Stanford University, where he was chairman of the computer science department. Dally and his Stanford team developed the system architecture, network architecture, signaling, routing and synchronization technology that is found in most large parallel computers today. Dally was previously at the Massachusetts Institute of Technology from 1986 to 1997, where he and his team built the J-Machine and the M-Machine, experimental parallel computer systems that pioneered the separation of mechanism from programming models and demonstrated very low overhead synchronization and communication mechanisms. From 1983 to 1986, he was at California Institute of Technology (CalTech), where he designed the MOSSIM Simulation Engine and the Torus Routing chip, which pioneered \u201cwormhole\u201d routing and virtual-channel flow control.<br \/>\n<a href=\"#top\">Back to top<\/a><\/p>\n<h4><strong><a id=\"panel\"><\/a>Panel<\/strong><\/h4>\n<p><em><strong>Massive-storage Networks vs Intensive-computing Networks<\/strong><\/em><br \/>\nModerator: John Kim,\u00a0<em>HP Labs \/ KAIST<\/em>, South Korea<\/p>\n<p><span style=\"text-decoration: underline;\">Panelists<\/span>:<\/p>\n<ul>\n<li>Dave Mayhew, San Diego University<\/li>\n<li>Bill Dally, NVIDIA and Stanford University<\/li>\n<li>Torsten Hoefler, ETH Zurich, Switzerland<\/li>\n<\/ul>\n<p><strong>Short Bios<\/strong><\/p>\n<p><a href=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/01\/dave-mayhew-e1485333669494.jpg\"><img decoding=\"async\" class=\"wp-image-114 alignleft\" src=\"http:\/\/hipineb.i3a.info\/hipineb2017\/wp-content\/uploads\/sites\/6\/2017\/01\/dave-mayhew-e1485333669494.jpg\" alt=\"dave-mayhew\" width=\"176\" height=\"224\" \/><\/a><\/p>\n<p><strong>David Mayhew<\/strong> is an experienced cyber security professional with over 35 years of applied experience and a PhD in Computer Engineering. Dr. Mayhew has a thorough background teaching all undergraduate level computer science courses as well as graduate courses. While working at AMD Dr. Mayhew pioneered an entirely new switch technology termed Server Aggregation Switch (SAW), which is a mechanism for building monolithic switches on a scale and speed that is otherwise impossible. Since then Mayhew has concentrated on a hardware acceleration strategy that focuses on the software aspects of reconfigurable logic usage. Dr. Mayhew authored \u201cEfficient C++: Performance Programming Techniques,\u201d and has over 35 patents granted or in process.<\/p>\n<p><a href=\"http:\/\/hipineb.i3a.info\/hipineb2016\/wp-content\/uploads\/sites\/4\/2015\/11\/hoefler_tree_full_style_small-e1450722953122.jpg\"><img loading=\"lazy\" decoding=\"async\" class=\"alignleft\" src=\"http:\/\/hipineb.i3a.info\/hipineb2016\/wp-content\/uploads\/sites\/4\/2015\/11\/hoefler_tree_full_style_small-e1450722953122.jpg\" alt=\"\" width=\"185\" height=\"240\" \/><\/a><\/p>\n<p><strong>Torsten Hoefler<\/strong> is an Assistant Professor of Computer Science at ETH Z\u00fcrich,\u00a0Switzerland. Before joining ETH, he led the performance modeling and\u00a0simulation efforts of parallel petascale applications for the NSF-funded\u00a0Blue Waters project at NCSA\/UIUC.\u00a0 He is also a key member of the\u00a0Message Passing Interface (MPI) Forum where he chairs the &#8220;Collective\u00a0Operations and Topologies&#8221; working group. Torsten won best paper awards at the ACM\/IEEE Supercomputing Conference SC10, SC13, SC14, EuroMPI\u00a02013, IPDPS 2015, and other conferences.\u00a0 He published numerous\u00a0peer-reviewed scientific conference and journal articles and authored\u00a0chapters of the MPI-2.2 and MPI-3.0 standards. He received the Latsis\u00a0award of ETH Zurich as well as an ERC starting grant in 2015. His\u00a0research interests revolve around the central topic of\u00a0&#8220;Performance-centric System Design&#8221; and include scalable networks,\u00a0parallel programming techniques, and performance modeling.\u00a0 Additional\u00a0information about Torsten can be found on his homepage at\u00a0<a href=\"http:\/\/htor.inf.ethz.ch\/\" target=\"_blank\" rel=\"noreferrer\">htor.inf.ethz.ch<\/a>.<br \/>\n<a href=\"#top\">Back to top<\/a><\/p>\n<h4><strong>Technical Paper Abstracts<\/strong><\/h4>\n<p><strong><a id=\"shpiner\"><\/a>Dragonfly+: Low Cost Topology for Scaling Data Centers<\/strong><br \/>\n<em>Alexander Shpiner, Zachy Haramaty, Saar Eliad, Vladimir Zdornov, Barak Gafni and Eitan Zahavi (Mellanox Technologies, Israel)<\/em><\/p>\n<p>Dragonfly topology was introduced by Kim et al. aiming to decrease the cost and diameter of the network. The topology divides routers into groups connected by long links. Each group strives to implement high-radix virtual router, connected by a completely-connected topology. In this paper, we propose an extended Dragonfly+ network in which routers inside the group are connected in Clos-like topology. Dragonfly+ is superior to conventional Dragonfly due to the significantly larger number of hosts which it is able to support. In addition, Dragonfly+ supports similar or better bisectional bandwidth for various traffic patterns, and requires smaller number of buffers to avoid credit loop deadlocks in lossless networks. Moreover, we introduce a novel Fully Progressive Adaptive Routing algorithm with remote congestion notifications. To support our proposal we present analytical analysis and simulations.<br \/>\n<a href=\"#top\">Back to top<\/a><\/p>\n<p><strong><a id=\"andujar\"><\/a>A case study on implementing virtual 5D torus networks using network components of lower dimensionality<\/strong><br \/>\n<em>Francisco Andujar-Mu\u00f1oz, Juan A. Villar, Jose L. Sanchez, Francisco Alfaro and Holger Fr\u00f6ning (University of Castilla-La Mancha, Spain, and Ruprecht-Karls University of Heidelberg, Germany)<\/em><\/p>\n<p>Several of the most powerful supercomputers in the Top500 and the Graph500 lists continue choosing a torus topology to interconnect a large number of compute nodes. In some cases, a torus network with five or six dimensions is implemented, however, one notices that the costs of implementing an interconnection network increase with the node degree. In previous works we defined and characterized the nD Twin (nDT) torus topology in order to virtually increase the dimensionality of a torus. This new topology reduces the distances between nodes and therefore increases network performance. In this work, we present how to build a 5DT torus network using commercial 6-port network cards. The main issues of this approach are detailed, and we present solutions these problems. Moreover we show, using the same components, that the performance of the 5DT torus network is higher than the performance of the 3D torus network for the same number of compute nodes.<br \/>\n<a href=\"#top\">Back to top<\/a><\/p>\n<p><strong><a id=\"belka\"><\/a>New link arrangements for Dragonfly networks<\/strong><br \/>\n<em>Madison Belka, Myra Doubet, Sofia Meyers, Rosemary Momoh, David Rincon-Cruz and David Bunde (Knox College, and\u00a0Columbia University, USA)<\/em><\/p>\n<p>Dragonfly networks have been proposed to exploit high-radix routers and optical links for high performance computing (HPC) systems. Such networks divide the switches into groups, with a local link between each pair of switches in a group and a global link between each group. Which specific switch serves as the endpoint of each global link is determined by the network\u2019s global link arrangement. We propose two new global link arrangements, each designed using intuition of how to optimize bisection bandwidth when global links have high bandwidth relative to local links. Despite this, the new arrangements generally outperform previously-known arrangements for all bandwidth relationships.<br \/>\n<a href=\"#top\">Back to top<\/a><\/p>\n<p><strong><a id=\"yebenes\"><\/a>An Effective Queuing Scheme to Provide Slim Fly topologies with HoL Blocking Reduction and Deadlock Freedom for Minimal-Path Routing<\/strong><br \/>\n<em>Pedro Yebenes Segura, Jesus Escudero-Sahuquillo, Pedro Javier Garcia, Francisco J. Quiles and Torsten Hoefler (University of Castilla-La Mancha and ETH Zurich, Switzerland)<\/em><\/p>\n<p>Interconnection network performance becomes a key issue in HPC systems as their size grows. In order to maximize network performance with the minimum quantity of network resources, Slim Fly topology was proposed. It offers a high network bandwidth and assures a network diameter of two. However, in congestion situations where the head-of-line blocking effect arises, the Slim Fly performance may drop dramatically. To alleviate this problem, we present first in this paper an analysis of congestion dynamics in Slim Fly networks. Then, based on this analysis, we propose the technique Slim Fly 2-Level Queuing (SF2LQ), especially designed for Slim Fly topologies using minimal-path routing. SF2LQ configures several virtual channels (VCs) grouped into two virtual networks to reduce HoL blocking while providing deadlock-free routing. This technique leverages the resources in network devices by efficiently using the available VCs. Finally, through simulation experiments, we show how our proposal boosts network performance while requiring a smaller number of VCs at input port buffers compared to with other techniques.<br \/>\n<a href=\"#top\">Back to top<\/a><\/p>\n<p><strong><a id=\"zahn\"><\/a>Early Experiences with Saving Energy in Direct Interconnection Networks<\/strong><br \/>\n<em>Felix Zahn, Steffen Lammel and Holger Fr\u00f6ning (<em>Ruprecht-Karls University of Heidelberg, Germany)<\/em><\/em><\/p>\n<p>Energy is emerging to become one of the most crucial factors in design decisions for future large scale computing systems. Especially Exascale-installations will have to operate within hard power and energy constraints. Besides economical reasons, power consumption is also limited by a limited power distribution, cooling capabilities, and minimization of carbon footprints. While other components, such as processors, become more and more energy-proportional, interconnects are still highly energy-disproportional. Although interconnection networks are contributing only about 10-20% to the overall power consumption of High-Performance Computing (HPC) or Cloud systems, this fraction is likely to increase significantly in the near future. Therefore, power saving strategies are mandatory for improving energy efficiency and thereby performance within hard power constraints. In this work, we introduce a simple energy saving strategy, which switches links on and off, depending on the user\u2019s performance constraints. Therefore, we adapted an existing OMNeT++ network simulator by adding new energy features. This simulator allows us to run traces of real world applications, including LULESH, NAMD, and Graph500 with different configurations. We show that this policy enables possible energy savings of up to 39% in interconnection networks. Furthermore, we demonstrate the impact of hardware design parameters, such as transition time, on possible power saving strategies.<br \/>\n<a href=\"#top\">Back to top<\/a><\/p>\n<p><strong><a id=\"benito\"><\/a>Extending commodity OpenFlow switches for large-scale HPC deployments<\/strong><br \/>\n<em>Mariano Benito, Enrique Vallejo, Ram\u00f3n Beivide and Cruz Izu (University of Cantabria, Spain, and\u00a0The University of Adelaide, Australia)<\/em><\/p>\n<p>Commodity Ethernet networks are used in many HPC systems. Extensions based on OpenFlow have been proposed for large HPC deployments, considering scalability and power consumption concerns. Such designs employ low-diameter topologies to minimize power consumption, such as Flattened Butterflies or Dragonflies. However, these topologies require non-minimal adaptive routing to deal with varying traffic characteristics and avoid pathological behaviors. The solutions to this issue in previous work relies on Ethernet Pauses to adapt minimal or non-minimal routing, depending on the availability (Pause status) of each corresponding output port. Nevertheless, such design provides an undesired high average latency under adversarial traffic patterns and a reduction in peak throughput under uniform traffic. This paper identifies the causes of the issues presented above, and presents a preliminary study of alternative solutions based on exploiting commodity congestion notification messages (QCN, 802.1Qau), currently available in Datacenter switches. This work presents the main differences between a congestion control mechanism such as QCN, which performs injection throttling reducing average network load, and an adaptive routing mechanism, which diverts traffic away from the congested area but increases average network load. In particular, it identifies the difficulty of separating the cases of uniform traffic at saturation and adversarial traffic at low loads.<br \/>\n<a href=\"#top\">Back to top<\/a><\/p>\n<p><strong><a id=\"perotin\"><\/a>Isolating jobs for security on high-performance fabrics<\/strong><br \/>\n<em>Matthieu P\u00e9rotin and Tom Cornebize (Atos, France, and\u00a0ENS Lyon, France)<\/em><\/p>\n<p>The various pieces of equipment in supercomputers are shared between jobs, that belong to different users. This situation raises security concerns. Jobs must not be able to conduct denial of service attacks targeting other jobs (voluntarily or accidentally). Moreover, job isolation must be guaranteed: unauthorized communication between two different jobs should not be allowed. However, high-performance interconnects are designed with performance as their main objective, and bypass the OS and its security models. In this paper, we show that by acting at the routing table level, it is possible to enforce job isolation without impacting job performance. Moreover, the isolation process can be dynamic, quick to set-up, with algorithms that are both independent from the routing algorithms and the interconnect topology.<br \/>\n<a href=\"#top\">Back to top<\/a><\/p>\n<p><strong><a id=\"shim\"><\/a>Knapp: A Packet Processing Framework for Manycore Accelerators<\/strong><br \/>\n<em>Junhyun Shim, Joongi Kim, Keunhong Lee and Sue Moon (SAP Labs Korea,\u00a0Lablup Inc. and KAIST, South Korea)<\/em><\/p>\n<p>High-performance network packet processing benefits greatly from parallel-programming accelerators such as Graphics Processing Units (GPUs). Intel Xeon Phi, a relative newcomer in this market, is a distinguishing platform because its x86-compatible vectorized architecture offers additional optimization opportunities. Its software stack exposes low-level communication primitives, enabling fine-grained control and optimization of offloading processes. Nonetheless, our microbenchmarks show that offloading APIs for Xeon Phi comes in short for combining low latency and high throughput for both I\/O and computation. In this work, we exploit Xeon Phi\u2019s low-level threading mechanisms to design a new offloading framework, Knapp, and evaluate it using simplified IP routing applications. Knapp lays the ground for full exploitation of Xeon Phi as a packet processing framework.<br \/>\n<a href=\"#top\">Back to top<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>The workshop will take place in\u00a0Hilton Austin,\u00a0500 E 4th St,\u00a0Austin, TX 78701. The room for the HiPINEB workshop will be 400\/402.\u00a0Speakers of Technical Sessions have 20 minutes for their presentations, plus 2 minutes for questions from the audience. 7:30 &#8211; <a class=\"more-link\" href=\"https:\/\/hipineb.i3a.info\/hipineb2017\/program\/\">Continue reading <span class=\"screen-reader-text\">  Program<\/span><span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_monsterinsights_skip_tracking":false,"_monsterinsights_sitenote_active":false,"_monsterinsights_sitenote_note":"","_monsterinsights_sitenote_category":0,"footnotes":""},"class_list":["post-89","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/hipineb.i3a.info\/hipineb2017\/wp-json\/wp\/v2\/pages\/89","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/hipineb.i3a.info\/hipineb2017\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/hipineb.i3a.info\/hipineb2017\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/hipineb.i3a.info\/hipineb2017\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/hipineb.i3a.info\/hipineb2017\/wp-json\/wp\/v2\/comments?post=89"}],"version-history":[{"count":55,"href":"https:\/\/hipineb.i3a.info\/hipineb2017\/wp-json\/wp\/v2\/pages\/89\/revisions"}],"predecessor-version":[{"id":186,"href":"https:\/\/hipineb.i3a.info\/hipineb2017\/wp-json\/wp\/v2\/pages\/89\/revisions\/186"}],"wp:attachment":[{"href":"https:\/\/hipineb.i3a.info\/hipineb2017\/wp-json\/wp\/v2\/media?parent=89"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}